1. Field of the Invention
The present invention relates to a solid imaging device and a driving method for the same.
2. Description of Related Art
A solid imaging device used to pick up an image in a scanner has pixels for a number corresponding to a maximum resolution. The resolution is reduced by combining adjacent pixels to a low resolution, thereby shortening an accumulation time.
FIG. 1 is a diagram illustrating a first example of a conventional solid imaging device. This solid imaging device includes photodiodes (i.e., photoelectric converting section) 1 for performing photoelectric conversion, a read gate electrode 20 for sending electric charges (CHG) obtained through the photoelectric conversion to a transfer electrode 21, a capacitance (Cfj) section 19 for converting the transferred electric charge into a voltage, an amplifier 13 for amplifying the voltage, and a reset gate 12 for drawing out the electric charge accumulated in the floating diffusion capacitance section 19 to a reset drain 11. Here, the transfer electrode 21 and a transfer electrode 22 constitute an electric charge transfer section.
FIGS. 2A to 2C illustrate an electric charge transferring process. Here, electric charges 23 are transferred from the photodiodes (i.e., photoelectric converting section) 1 to the transfer electrode 21 through the read gate electrode 20 from FIG. 2A to FIG. 2B, and thereafter, the electric charge 23 is transferred from the transfer electrode 21 to the transfer electrode 22 from FIG. 2B to FIG. 2C.
FIG. 3 is timing charts illustrating standard timings at which the charges in all of pixels are outputted. FIG. 4 illustrates timings in a low resolution drive in case of coupling the charges in four pixels. Here, a resolution is one fourth of a standard resolution. The frequency of a transfer clock signal in the electric charge transfer section is quadruple of that of the standard clock signal in order to make a data rate equal to that at the standard timings illustrated in FIG. 3. At this time, the coupling of the charges in the four pixels is performed in the floating diffusion capacitance section 19.
Referring to FIGS. 3 and 4, a transfer gate clock signal φTG is supplied to the read gate electrode 20. A reset clock signal φR is supplied to the reset gate 12. A drive clock signal φ1 is supplied to the transfer electrode 21, and a drive clock signal φ2 is supplied to the transfer electrode 22. Vout denotes an output of the amplifier 13.
FIG. 5 is a diagram illustrating a second example of a conventional solid imaging device. This solid imaging device includes photodiodes (i.e., a photoelectric converting section) 1 for performing photoelectric conversion, a read gate electrode 26 for sending an electric charge obtained through the photoelectric conversion to memory regions (i.e., electric charge accumulating sections) 15, a read gate electrode 24 and a read gate electrode 25 for sending the electric charge accumulated in the memory regions 15 to a transfer electrode 21, a floating diffusion capacitance section 19 for converting the transferred electric charge into voltage, the amplifier 13 for amplifying the voltage, and a reset gate 12 for drawing out the electric charge accumulated in the floating diffusion capacitance section 19 to a reset drain 11. Here, a pair of the transfer electrodes (i.e., the transfer electrode 21 and the transfer electrode 22) is assigned to two photodiodes 1 in the photoelectric converting section. Therefore, since the number of the transfer electrodes is less by a half when all of signals are outputted, a read operation is performed twice.
In this case, the charges in odd-numbered pixels are first transferred, and then the charges in even-numbered pixels are transferred, as illustrated in FIGS. 6A to 6G. The transfer timings at that time are illustrated in FIG. 7. In FIGS. 6A and 6B, the electric charges a to h are transferred from the photodiodes 1 in a photoelectric converting section to the memory regions 15 via the gate electrode 26. In FIGS. 6B and 6C, the electric charges a, c, e and g are transferred from the memory regions 15 to the transfer electrodes 21 via the gate electrodes 24. In FIGS. 6C and 6D, the electric charge a is transferred from the transfer electrode 21 to the adjacent floating diffusion capacitance section 19, and further the electric charges c, e and g are transferred from the transfer electrodes 21 to the adjacent transfer electrodes 22 on the side of the floating diffusion capacitance section 19. The above-described transfer is repeated until all of the electric charges a, c, e and g are drawn to the reset drain 11, as illustrated in FIG. 6E. In FIGS. 6E and 6F, the electric charges b, d, f and h are transferred from the memory regions 15 to the transfer electrodes 21 via the gate electrodes 25. In FIGS. 6F and 6G, the electric charge b is transferred from the transfer electrode 21 to the adjacent floating diffusion capacitance section 19, and further the electric charges d, f and h are transferred from the transfer electrodes 21 to the adjacent transfer electrodes 22 on the side of the floating diffusion capacitance section 19. Hereinafter, the above-described transfer is repeated until all of the electric charges b, d, f and h are drawn to the reset drain 11.
An advantage of this structure is in that in case of 2-pixel coupling, electric charges can be coupled on each transfer electrode 21 by turning on the read gate electrodes 24 and the read gate electrodes 25 at a same time. As a result, a same data rate as that of the standard timings can be achieved without increasing the frequencies of the clock signals applied to the transfer electrodes 21 and the transfer electrodes 22. Such timings are illustrated in FIG. 8. The frequencies of the clock signals needs to be increased in case of coupling the charges in 4 or more pixels, and such timings are illustrated in FIG. 9.
Referring to FIGS. 7 to 9, a reset pulse φR is supplied to the reset gate 12. A drive clock signal φ1 is supplied to the transfer electrode 21, and a drive clock signal φ2 is supplied to the transfer electrode 22. A transfer gate clock signal φTG1 is supplied to the read gate electrode 26. A transfer gate clock signal φTG2-1 is supplied to the read gate electrode 24, and a transfer gate clock signal φTG2-2 is supplied to the read gate electrode 25. Vout denotes an output from the amplifier 13.
Although a mount of charges equal to an amount of charges in high resolution can be accumulated in a short period of time by coupling electric charges of adjacent pixels even at reduced resolutions, the data rate is decreased unless a transfer speed is increased. As a result, the transfer speed is doubled every time the resolution is halved in the first example of the solid imaging device. As a consequence, a high-frequency clock signal is needed in the system. High-frequency noise is generated more easily which causes EMI (electro magnet interference).
The same problem is caused in FIG. 5 when the resolution is gradually decreased. If the problem is intentional to be eliminated by increasing the number of photodiodes, an output order of data in each of resolutions becomes complicated, thereby raising another problem of the increase in the number of read gates.
In conjunction with the above description, an imaging device is disclosed in Japanese Patent Application Publication No. (JP-P2007-027456A). This imaging device includes a plurality of pixels aligned in one line, a read gate adjacent to the plurality of pixels, memory gates disposed in correspondence to the plurality of pixels adjacently to the read gate, memory control gates disposed in correspondence to the memory gates, and a CCD (charge coupled device) accumulating gate disposed commonly to the plurality of memory control gates.
Also, Japanese Patent Application Publication (JP-A-Heisei 8-205034) discloses a technique to temporarily save electric charges staying heretofore in a horizontal electric charge transfer section or a vertical electric charge transfer section so as to rapidly read arbitrary electric charge data. For example, the horizontal electric charge transfer section includes a first electric charge transfer section for accumulating electric charge held in the vertical electric charge transfer section and a second electric charge transfer section for accumulating the electric charge held in the first electric charge transfer section, and the electric charges are circulated in a ring manner at a constant speed between the first and second electric charge transfer sections. However, the first and second electric charge transfer sections are driven in association with each other. In other words, a same clock signal is supplied to both of the first and second electric charge transfer sections, and therefore, they cannot be driven at different timings or in different cycles.